1.Eachportcansendandreceiveeightqueue2.Upto86piecesofqueuereceivertoadjust
(RSS)inmultipleprocessorsystemcanminimizetheuseoftheCPU3.Support8poolofeach
port‘s(asinglequeue)virtualmachinedevicequeue(VMDq)4.SupporttheSR-IOVfunction5.
Supportdirectcacheaccess(DCA)6.SupporttheIntelI/OV3.0accelerationtechnology7.TSO
interleavedtechniqueistoreducethedelay
8.TominimizetheequipmentI/OinterruptusingMSIandMSI-X
9.TheUDPandTCPandIPchecksumpartialload
10.TheUDPandTCPsendpiecewiseload(TSO)
11.SCTPreceivingandsendingcheckandpartialload
12.Thepacketcombinationofinterruptandtimer(packettimer)andabsolute-interruptiondelay
timeristosendandreceiveoperation
13.SupportPCIExpessbasespecification2.0(5GTs)
14.IntelI350AM4doubleintegratedMAC+PHYandSERDESchipcontrollerwithhighperformance,highreliabilityandlowpowerconsumptioncharacteristics
15.Superdepth,basedonthepacketbufferperchannelcanreducetheuseoftheCPU
16.Hardwareaccelerationcanbepartialloadtaskfromthemainprocessor.ThecontrollercanbeusedforpartialloadTCP/UDP/IPchecksumTCPsegment17.Serverlevelofreliability,availabilityandperformancecharacteristics:linkaggregationandloadbalancingRelevantswitches:802.3AD(LACP),commonTrunking(GEC/FEC)ExchangeandNICnorelatedfailoverPrioritization-802.1player2prioritycodingVirtuallocalareanetwork(LAN)802.1qVLANLargeframe(9.5KB)802xflowcontrolMulticast/broadcastpacketreplication